1. Field of the Invention
This invention relates to the making of electronic components such as integrated circuit semiconductor devices having electrical interconnection structures within the component and, more particularly, to a reactive barrier/seed pre-cleaning method for a dual damascene copper process.
2. Description of Related Art
Multi-layer electronic components offer an attractive packaging solution for high performance systems such as in computer, telecommunications, military, and consumer applications. These electronic components offer high-density interconnections and the ability to provide increased circuitry for a given electronic component size. For convenience, the following description will be directed to a dual damascene fabrication process for making integrated circuit components.
In general, multilayer electronic components made using a damascene or dual damascene process comprise multiple layers of a dielectric material having vias, trenches and other openings in the dielectric layer extending from one layer to another layer. These openings are filled with a conductive material and electrically connect the metallization in one layer to the metallization in another layer and provide for the high density electronic components devices now used in industry.
An important aspect of dual damascene multilayer electronic components are vias or openings between layers in which a conductive material is filled to provide electrical contact between the metallization in the different layers. Broadly stated, the typical multilayer electronic component is built up from a number of layers of a dielectric material layer such as silicon dioxide, fluorinated silicon oxide, polymers including polyimide and fluorinated polyimide, ceramics, carbon and other such dielectric materials. In the processing sequence known in the art as the “Damascene Process”, the dielectric layer is patterned using known techniques such as the use of a photoresist material which is exposed to define the wiring pattern. After developing, the photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. Using the Damascene Process, openings defining wiring patterns are provided in the dielectric layer, extending from one surface of the dielectric layer to the other surface of the dielectric layer. These wiring patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process may include planarization of the metal by removing excess material with a method such as chemical mechanical polishing.
In the Single Damascene Process, vias or openings are provided in the dielectric layer and filled with metallization to provide electrical contact between layers of wiring levels. In the Dual Damascene Process, the via openings and the wiring pattern openings are both provided in the same dielectric layer before filling with metallization. This process simplifies the procedure and eliminates some internal interfaces. These procedures are continued for each layer in the electronic component until the multilayer electronic component is completed.
In FIG. 1, a dual Damascene line and interconnection of the prior art is shown. A substrate 11 has a dielectric layer 12 thereon with a copper layer 13 formed therein. Another dielectric layer 14 is formed on the dielectric layer 12 and a portion removed by etching to form a via opening 15 and a trench opening 16. The via opening 15 and trench opening 16 together form a dual damascene opening for exposing part of the copper layer 13 and for interconnecting with the copper layer.
The dielectric material used to form the layers provides electrical insulation and electrical isolation between the copper wiring elements. To avoid metal diffusion between the copper wiring elements and the dielectric, barrier layers, also referred to as liners, are included in the structure to contain the copper or other metal and to provide improved adhesion of the copper lines and vias to the dielectric or other metallization.
The barrier layer is typically a refractory metal such as Ta or TaN and presents a barrier to the diffusion of copper metal between the via and trench and the dielectric but also presents a barrier between the copper metal and the metallization of the underlying or overlying conductor wiring levels. Typically, the barrier layer is formed in the via and trench on both sidewalls and at the base of the via to form the barrier layer.
In a damascene process, it is always necessary to provide a pre-clean process prior to barrier layer and/or metal deposition of the via and/or via/trench interconnection. As shown in FIG. 1, copper oxides always form at the bottom of a damascene via and/or via/trench because of the opening to the underlying copper layer which exposed copper oxidizes in air. As shown in FIG. 1, a copper oxide film 18 is formed on the surface of the copper conductor layer 13 in dielectric layer 12. Copper oxide is detrimental to the integrated circuit (IC) device and must be removed before further processing.
Etching and stripping cleaning processes may leave residues and a conventional pre-clean process uses argon to sputter the bottom to remove residue and copper oxides. The use of argon however, has a tendency to resputter copper onto the damascene sidewall which causes copper out-diffusion into the dielectric layers. Furthermore, argon has been found to damage the insulation effect of the dielectric especially when low-k materials are used.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for cleaning exposed copper surfaces when making electronic devices and, in particular, when using a single Damascene process or a dual Damascene process.
Another aspect of the invention is to provide electronic components made using the method of the invention.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.